Nagesh/B.Tech

                                                http://www.linkedin.com/in/mnagesh

Nagesh Machupalli

Email: machupallinagesh@gmail.com

Mobile: +91 97382 63020                                                                                                                  

Objective:

To utilize, develop my technical expertise and align with company goals and work with global clients.

Proficient:

• Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog.
• Expertise with  TLM, OVM, UVM verification environment. 
• Good understanding of the ASIC and FPGA design flow and Digital Design.
• Expertise in RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis.

VLSI Domain Skill set:

HDLs                                        : Verilog and VHDL

HVL                                          : System Verilog and SVA

Verification Methodologies    : Coverage Driven Verification, Assertion Based Verification,

                                                       Transaction Based Verification, Constrained Random Verification

TB Methodology                      : OVM, UVM

EDA Tool                                 : Modelsim and ISE    

Scripting language                  : Perl

Programming skills                    : C, C++, MATLAB

Academic:

Name of the Degree	Institution/University	Year of passed out	Aggregate percentage
B.Tech in Electronics and Communication.	JNTU, Anantapur	2012	63.98%
12th in Mathematics, Physics and Chemistry	Board of Intermediate Education, AP.	2008	91.20%
10th (SSC)	A.P.R School Sri Sailam, AP	2006	87.00%

Experience and Certificates:

Certification in Advanced VLSI Design and Verification from Maven Silicon (Jul-Oct 2012)

Achievements:

·           Certificated in XII NATIONAL MATHS OLYMPIAD.

·           Received the Best performer award from Maven Silicon during the VLSI Design course

PROJECT PROFILES:

Name#1: SPI Controller Core - Verification (Oct’2012)

Methodology:  OVM

EDA Tools and Environment: Modelsim, Questa -- Verification Platform

Description: The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register.

Responsibilities and Achievements: 

·           Architected the class based verification environment using OVM

·           Verified the RTL module using OVM

·           Generated functional and code coverage for the RTL verification sign-off

Name#2: Dual Port RAM –RTL design and verification (Sep’2012)  

HDL: Verilog

Methodology:  OVM

EDA Tools and Environment: Modelsim, Questa – Verification Platform and ISE

Responsibilities and Achievements: 

·        Implemented the Dual Port Ram using Verilog HDL independently

·        Architected the class based verification environment using System Verilog

·        Verified the RTL module using System Verilog 

·        Generated functional and code coverage for the RTL verification sign-off

Name#3: Real Time Clock – RTL design and verification (Aug’2012)

HDL: Verilog

HVL: System Verilog

EDA Tools and Environment: Modelsim, Questa – Verification Platform and ISE

Responsibilities and Achievements: 

·           Implemented the Real Time Clock using Verilog HDL independently

·           Architected the class based verification environment using SystemVerilog

·           Verified the RTL model using SystemVerilog.

·           Generated functional and code coverage for the RTL verification sign-off

·           Synthesized the design

(m nagesh)                                                                                                       16/10/2012