vlsi-resumes

Tuesday, 25 December 2012

Posted by Nagesh at 07:20

Labels: Above 2-Exp

Nagesh: • Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog. • Expertise with TLM, OVM, UVM verification environment. • Good understanding of the ASIC and FPGA design flow and Digital Design. • Expertise in RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. Verification Methodologies: Coverage Driven Verification, Assertion Based Verification, Transaction Based Verification, Constrained Random Verification

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